1. Field of the Invention
The present invention relates to semiconductor integrated circuits and, in particular to a differential output stage that reduces the idle current consumed by the output stage when its differential inputs are substantially equal.
2. Description of the Related Art
A differential output stage is an amplifier circuit which generates a differential signal in response to a pair of input signals. In a local area network defined by the IEEE 802.3 standard, the input signals include a Manchester-encoded data signal Vin+ and a complementary Manchester-encoded data signal Vin-.
In integrated circuit applications, the differential signal is typically generated by driving a current across a low-impedance external resistor in one direction when the difference between the data signal Vin+ and the complementary data signal Vin- is positive and by driving a current across the low-impedance external resistor in the opposite direction when the difference between the data signal Vin+ and the complementary data signal Vin- is negative.
FIG. 1 shows a conventional integrated circuit differential output stage 1 connected to an external resistor network 2. The conventional differential output stage 1 typically consists of both a npn forward transistor 3 and a npn reverse transistor 4. As shown in FIG. 1, the base of the forward transistor 3 is connected to receive the data signal Vin+ while the base of the reverse transistor 4 is connected to receive the complementary data signal Vin-.
The external resistor network 2 includes a forward resistor 5 which is connected between the emitter node of the forward transistor 3 and ground, a reverse resistor 6 which is connected between the emitter node of the reverse transistor 4 and ground, and a difference resistor 7 which is connected between the emitter node of the forward transistor 3 and the emitter node of the reverse transistor 4. The forward transistor 3 and the reverse transistor 4 as well as the forward resistor 5 and the reverse resistor 6 are generally matched.
The output stage 1 shown in FIG. 1 operates by oppositely varying the base-emitter voltages of the forward transistor 3 and the reverse transistor 4. When the difference between the data signal Vin+ and the complementary data signal Vin- is positive, the base-emitter voltage of the forward transistor 3 increases, thereby generating more current, while the base-emitter voltage of the reverse transistor 4 decreases, thereby generating less current. This produces a voltage differential across the difference resistor 7 which causes a current to flow across the difference resistor 7 from the emitter node of the forward transistor 3 to the emitter node of the reverse emitter transistor 4, thereby generating a positive differential signal.
Similarly, when the difference between the data signal Vin+ and the complementary data signal Vin- is negative, the base-emitter voltages of the forward transistor 3 and the reverse transistor 4 are reversed. This condition causes a current to flow across the difference resistor 7 from the reverse emitter node to the forward emitter node, thereby generating a negative differential signal.
When, however, the voltage of the data signal Vin+ and the complementary data signal Vin- are substantially equivalent, both the forward transistor 3 and the reverse transistor 4 are biased to output a substantially equivalent idle current. Since the forward and reverse transistors (3, 4) and the forward and reverse resistors (5, 6) are matched, the voltage at the emitter nodes of both the forward transistor 3 and the reverse transistor 4 are approximately equivalent. Thus, substantially no current flows across the difference resistor and no differential signal is generated.
Although substantially no current flows across the external difference resistor 7 when the data signal Vin+ and the complementary data signal Vin- are equivalent, the idle current generated by both the forward and the reverse transistors (3, 4) continuously flows across the forward and reverse resistors (5, 6), respectively. When the output stage 1 is utilized to drive the differential signal onto a local area network defined by the IEEE 802.3 standard, the combined idle current generated by both the forward transistor 3 and reverse transistor 4 is typically on the order of 52 milliamperes.
Thus, the output stage 1 consumes a significant quantity of power when the differential signal is not generated. Therefore, there is a need for a differential output stage that consumes less current in the idle mode.